1. Field of Invention
The present invention relates to semiconductor device fabrication; more particularly, the present invention relates to a test structure for wafer acceptance test (WAT) and a test process for probecard needles.
2. Description of Related Art
Wafer-level test plays an essential role in semiconductor device fabrication. By the testing, defective dices (chips) are identified and may be discarded before they undergo the post-processing, thereby reducing the waste of cost. Being one of such wafer-level tests, the wafer acceptance test includes various electrical tests on the pads disposed around the peripheral regions of a dice. The main purposes of the wafer acceptance test are to confirm the reliability of the fabrication process and to enhance the yield of dices.
Wafer acceptance test may be conducted via a probecard with a plurality of probecard needles. Upon testing of a single wafer, the probecard may contact the wafer for tens of thousand times. A common issue arises when a probecard needle deforms, deviates from its original position, or is blunted as a result of the mechanical impact of the contacts. If a probecard needle is in its anomalous state (e.g. deformed, deviated from the original position, or blunted), it may damage the other components such as metal routing on the wafer during the subsequent tests. There is thus a need for a test process for the normality of the probecard.